Traditionally an n+ polysilicon pre-gate etch doping mask has been used to raise the dopant level in the polysilicon above the dopant level provided by the source/drain implant to improve NMOS transistor performance. In such a flow, following polysilicon deposition, an n+ poly pre-gate etch doping mask is used for protecting/covering the poly regions corresponding to the PMOS area, and an n-type dopant (e.g. P or As) is implanted into the polysilicon gates corresponding to the NMOS area. A dopant anneal may or may not follow the n-type poly pre-gate doping. A gate etch step then follows to define the n-doped polysilicon gates for the NMOS and undoped polysilicon gates for the PMOS. The pre-gate etch implant can result in creation of an unintended CD differential between PMOS (undoped poly) and NMOS (heavily doped poly) due to resulting poly etch rate differences.
As known in the art, TOXINV, which may also be referred to as inversion TOX, refers to the loss of inversion charge and therefore transconductance due to inversion-layer quantization and polysilicon-gate depletion effects. Quantum mechanic considerations dictate that the density of inversion electrons peaks at approximately 1 nm below the polysilicon surface, which effectively reduces the gate capacitance and therefore the inversion charge in the case of an oxide dielectric to those of an equivalent oxide dielectric about 0.4 nm thicker than the physical gate dielectric (e.g. oxide). Similarly, depletion effects occur in polysilicon in the form of a thin space-charge layer near the dielectric interface which acts to reduce the gate capacitance and inversion-charge density for a given gate drive condition. The percentage of gate-capacitance attenuation is known to become more significant as the dielectric thickness is reduced. For example, for a polysilicon doping level of 1020 cm−3, a 2-nm oxide dielectric loses about 20% of the inversion charge at 1.5-V gate voltage because of the combined effects of polysilicon gate depletion and inversion-layer quantization. Using n-type dopant in n-type polysilicon for NMOS transistors above levels provided by source/drain implantation is known to provide a reduced TOXINV, which in turn can improve NMOS performance.
CMOS logic gates used in a wide variety of CMOS circuits are all generally based on the static inverter. FIG. 1 a schematic of a conventional static CMOS inverter circuit 10. Both transistors in the inverter circuit 10 are generally enhancement-mode MOSFETs; NMOS 12 with its source grounded, and PMOS 11 with its source connected to Vdd. Their respective gates are connected together to form the input, shown as A, generally coupled together using a polysilicon line 15, and their drains are connected together to form the output, shown as Q. During their respective source/drain implants, the gate electrode of the PMOS 11 is doped p+, while the gate of the NMOS 12 is doped n+. A silicide or other shunting layer is generally used to short the n+/p+ diode formed by the polysilicon line 15 coupling the gates of PMOS 11 and NMOS 12.
As known in the art, the inverter circuit 10 is used in logic gates other than the inverter, such as for NOR and NAND circuits, by combining inverter circuits in a partially series or partially parallel structure, and in other circuits such as certain latches. Regarding latches, for example, a master-slave D flip-flop includes a CMOS inverter to invert the enable input applied to the master for application to the slave.
Moreover, certain high density circuits having a large number transistors from complex microprocessor integrated circuits to signal processing and communication circuits generally include CMOS inverters. For example, the Arithmetic and Logic Unit (ALU) for a Microprocessor generally includes CMOS logic gates, including a plurality of CMOS inverters.
Another example of an integrated circuit that includes CMOS inverters is a static ram (SRAM), which generally uses a pair of cross coupled inverters in the bit cells. For example, for integrated circuits that include conventional 5T or 6T SRAM cells, the p+ poly gates of the PMOS load (pull-up) and the n+ poly gates of the NMOS driver (pull-down) are coupled by an n+ polysilicon line. Silicide or another conductor is generally used to short the n+/p+ diode formed.
Yet another example of an integrated circuit that uses CMOS inverters is a dynamic RAM (DRAM). The sense amplifier in a DRAM is typically essentially a pair of cross-connected inverters between the bit lines. That is, the first inverter is connected from the + bit line to the − bit line, and the second is connected from the − bit line to the + bit line.
In certain circuits n+ poly doping can result in counterdoping the p+ doped PMOS gate. For example, as described above, in SRAM cells, the inverters in the memory cell generally have their poly gates coupled using a polysilicon line. With the polysilicon coupling lines n+ doped by the pre-gate etch n-type implant generally provided on SRAMs, the PMOS load transistor can experience significant and locally variable gain boundary cross-diffusion from the n+ dopant from conventional activation/annealing processes, particularly when phosphorous is used as the n-type dopant. As a result, the PMOS load transistors can suffer a significant increase in TOXINV which can be locally variable, with a resulting degradation in PMOS performance, such as by degrading VTLIN/VTSAT control, increasing VTLIN/VTSAT variability, and degrading IDSAT device performance. Local VTLIN variation (VT mismatch) in adjacent bit cell transistors can also become a problem, leading to degraded cell stability.
Scaling can exacerbate this counter doping problem. When design rules shrink, the n-poly mask edge to the n-well boundary spacing shrinks. If n+ poly mask/implants are used in SRAM bit cell NMOS transistors to improve NMOS performance, the PMOS load (pull-up) transistor will increasingly get n-type dopant counter-doping its polysilicon gate, degrading the PMOS transistors in the memory cell.